RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

2.7.1. Dynamic Transceiver Reconfiguration Controller

RapidIO II IP core variations that target an Arria® V, Arria® V GZ, Cyclone® V, Stratix® V device require an external reconfiguration controller to function correctly in hardware. RapidIO II IP core variations that target an Intel® Arria® 10, Intel® Stratix® 10 or Intel® Cyclone® 10 GX device include a reconfiguration controller block and do not require an external reconfiguration controller. However, you need to control dynamic transceiver reconfiguration in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX devices through dynamic reconfiguration interface if you turn on that interface in the RapidIO II parameter editor.

Keeping the reconfiguration controller external to the IP core in these devices provides the flexibility to share the reconfiguration controller among multiple IP cores and to accommodate FPGA transceiver layouts based on the usage model of your application. In Intel® Arria® 10 and Intel® Stratix® 10 devices, you can configure individual transceiver channels flexibly through an Avalon® -MM transceiver reconfiguration interface.

Intel® recommends that you implement the reconfiguration controller using the Transceiver Reconfiguration Controller. The Transceiver Reconfiguration Controller performs offset cancellation during bring-up of the transceiver channels.

The Transceiver Reconfiguration Controller is available in the IP catalog. You must add it to your design and connect it to the RapidIO II IP core reconfiguration signals.

In the Transceiver Reconfiguration Controller parameter editor, you select the features of the transceiver that can be dynamically reconfigured. However, you must ensure that the following two features are turned on:
  • Enable PLL calibration
  • Enable Analog controls
An informational message in the RapidIO II parameter editor tells you the number of reconfiguration interfaces you must configure in your dynamic reconfiguration block.
The Reconfiguration Controller communicates with the RapidIO II IP core on two buses:
  • reconfig_to_xcvr (output)
  • reconfig_from_xcvr (input)
Each of these buses connects to the bus of the same name in the RapidIO II IP core. You must also connect the following Reconfiguration Controller signals:
  • mgmt_clk_clk
  • mgmt_rst_reset
  • reconfig_busy

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