RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

2.6.4. Simulating the Testbench with the Xcelium Parallel Simulator

To simulate the RapidIO II IP core testbench using the Cadence Xcelium* parallel simulator, perform the following steps:

  1. Change directory to the directory where the testbench simulation script is located:
    • For Intel® Arria® 10, Intel® Stratix® 10 variations, change directory to <your_ip>/sim/cadence.
    • For all other device variations you generate from the Intel® Quartus® Prime IP Catalog, change directory to <your_ip>_sim/xcelium.
    • For all other device variations you generate from the Platform Designer IP Catalog, change directory to <Qsys_system or your_ip>/simulation/xcelium.
  2. Type the following command:
    sh xcelium_setup.sh TOP_LEVEL_NAME="tb_rio" USER_DEFINED_SIM_OPTIONS="-input\ \"@run\ 2ms\;\ exit\""
    

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