RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.3.2. Maintenance Interface Signals5.3.1.4. Maintenance Interface Signals

Table 22.  Maintenance Avalon-MM Slave Interface Signals
Signal Direction Description
mnt_s_waitrequest Output Maintenance slave wait request.
mnt_s_read Input Maintenance slave read request.
mnt_s_write Input Maintenance slave write request.
mnt_s_address[23:0] Input Maintenance slave address bus. The address is a word address, not a byte address.
mnt_s_writedata[31:0] Input Maintenance slave write data bus.
mnt_s_readdata[31:0] Output Maintenance slave read data bus.
mnt_s_readdatavalid Output Maintenance slave read data valid.
mnt_s_readerror Output Maintenance slave read error, which indicates that the read transfer did not complete successfully. This signal is valid only when the mnt_s_readdatavalid signal is asserted.
The Maintenance module supports an interrupt line, mnt_mnt_s_irq, on the Register Access interface. When enabled, the following interrupts assert the mnt_mnt_s_irq signal:
  • Received port-write.
  • Various error conditions, including a MAINTENANCE read request or MAINTENANCE write request that targets an out-of-bounds address.
Table 23.  Maintenance Avalon-MM Master Interface Signals
Signal Direction Description
usr_mnt_waitrequest Input Maintenance master wait request.
usr_mnt_read Output Maintenance master read request.
usr_mnt_write Output Maintenance master write request.
usr_mnt_address[31:0] Output Maintenance master address bus.
usr_mnt_writedata[31:0] Output Maintenance master write data bus.
usr_mnt_readdata[31:0] Input Maintenance master read data bus.
usr_mnt_readdatavalid Input Maintenance master read data valid.

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