RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.1.1. Avalon® -MM Master and Slave Interfaces

The Avalon® -MM master and slave interfaces execute transfers between the RapidIO II IP core and the system interconnect. The system interconnect allows you to use the Platform Designer system integration tool to connect any master peripheral to any slave peripheral, without detailed knowledge of either the master or slave interface. The RapidIO II IP core implements both Avalon® -MM master and Avalon® -MM slave interfaces.

Avalon® -MM Interface Byte Ordering

The RapidIO protocol uses big endian byte ordering, whereas Avalon® -MM interfaces use little endian byte ordering. No byte- or bit-order swaps occur between the 64-bit Avalon® -MM protocol and RapidIO protocol, only byte- and bit-number changes. For example, RapidIO Byte0 is Avalon® -MM Byte7, and for all values of i from 0 to 63, bit i of the RapidIO 64-bit double word[0:63] of payload is bit (63-i) of the Avalon® -MM 64-bit double word[63:0].

Table 10.  Byte Ordering
Protocol Byte Lane (Binary)
1000_0000 0100_0000 0010_0000 0001_0000 0000_1000 0000_0100 0000_0010 0000_0001
RapidIO Protocol (Big Endian) Byte0 [0:7] Byte1 [0:7] Byte2 [0:7] Byte3 [0:7] Byte4 [0:7] Byte5 [0:7] Byte6 [0:7] Byte7 [0:7]
32-Bit Word[0:31]

wdptr = 0

32-Bit Word[0:31]

wdptr = 1

Double Word[0:63]

RapidIO Byte Address N = {29'hn, 3'b000}

Avalon® - MM Protocol (Little Endian) Byte7 [7:0] Byte6 [7:0] Byte5 [7:0] Byte4 [7:0] Byte3 [7:0] Byte2 [7:0] Byte1 [7:0] Byte0 [7:0]
Address = N+7 Address = N+6 Address = N+5 Address = N+4 Address = N+3 Address = N+2 Address = N+1 Address = N
32-Bit Word[31:0]

Avalon® -MM Byte Address = N+4

32-Bit Word[31:0]

Avalon® -MM Byte Address = N

64-bit Double Word0[63:0]

Avalon® -MM Byte Address = N

In variations of the RapidIO II IP core that have 128-bit wide Avalon® -MM interfaces, the least significant half of the Avalon® -MM 128-bit word corresponds to the 8-byte double word at RapidIO address N, and the most significant half of the Avalon® -MM 128-bit word corresponds to the 8-byte double word at RapidIO address N+8. If two 8-byte double words appear in the RapidIO packet in the order dw0, followed by dw1, they appear on the 128-bit Avalon® -MM interface as the 128-bit word {dw1, dw0}.

Table 11.  Double-Word Ordering in a 128-Bit Avalon® -MM Interface
Protocol Avalon® -MM Interface
RapidIO Protocol (Big Endian) Second Transmitted Double Word[0:63]

RapidIO Byte Address N + 8

First Transmitted Double Word[0:63]9

RapidIO Byte Address N = {29'hn, 3'b000}

Avalon® -MM Protocol (Little Endian) 64-Bit Double Word[63:0]

Avalon® -MM Byte Address = N+8

64-Bit Double Word[63:0]

Avalon® -MM Byte Address = N

9 Bit 0 of the RapidIO double word is transmitted first on the RapidIO link.

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