RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.2.1. Avalon System Clock

The Avalon system clock, sys_clk, is an input to the RapidIO II IP core that drives the Transport and Logical layer modules and most of the Physical layer module.
Note: You must drive the sys_clk clock from the same source from which you drive the tx_pll_refclk input clock.

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