RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.1.2. Register Access Interface Signals5.3.1.1. Register Access Interface Signals

Table 62.  Register Access Avalon-MM Slave Interface Signals
Signal Direction Description
ext_mnt_waitrequest Output Register Access slave wait request. The RapidIO II IP core uses this signal to stall the requestor on the interconnect.
ext_mnt_read Input Register Access slave read request.
ext_mnt_write Input Register Access slave write request.
ext_mnt_address[21:0] Input Register Access slave address bus. The address is a word address, not a byte address.
ext_mnt_writedata[31:0] Input Register Access slave write data bus.
ext_mnt_readdata[31:0] Output Register Access slave read data bus.
ext_mnt_readdatavalid Output Register Access slave read data valid signal supports variable-latency, pipelined read transfers on this interface.
ext_mnt_readresponse Output Register Access read error, which indicates that the read transfer did not complete successfully. This signal is valid only when the ext_mnt_readdatavalid signal is asserted.
std_reg_mnt_irq Output Standard registers interrupt request. This interrupt signal is associated with the error conditions registered in the Command and Status Registers (CSRs) and the Error Management Extensions registers.
io_m_mnt_irq Output I/O Logical Layer Avalon-MM Master module interrupt signal. This interrupt is associated with the conditions registered in the Input/Output Master Interrupt register at offset 0x103DC.
io_s_mnt_irq Output I/O Logical Layer Avalon-MM Slave module interrupt signal. This interrupt signal is associated with the conditions registered in the Input/Output Slave Interrupt register at offset 0x10500.
mnt_mnt_s_irq Output Maintenance slave interrupt signal. This interrupt signal is associated with the conditions registered in the Maintenance Interrupt register at offset 0x10080.
The interface supports the following interrupt lines:
  • std_reg_mnt_irq — when enabled, the interrupts registered in the CSRs and Error Management registers assert the std_reg_mnt_irq signal.
  • io_m_mnt_irq — this interrupt signal reports interrupt conditions related to the I/O Avalon-MM master interface. When enabled, the interrupts registered in the Input/Output Master Interrupt register at offset 0x103DC assert the io_m_mnt_irq signal.
  • io_s_mnt_irq — this interrupt signal reports interrupt conditions related to the I/O Avalon-MM slave interface. When enabled, the interrupts registered in the Input/Output Slave Interrupt register at offset 0x10500 assert the io_s_mnt_irq signal.
  • mnt_mnt_s_irq — this interrupt signal reports interrupt conditions related to the Maintenance interface slave port. When enabled, the interrupts registered in the Maintenance Interrupt register at offset 0x10080 assert the mnt_mnt_s_irq signal.

Did you find the information on this page useful?

Characters remaining:

Feedback Message