RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents
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4.3.1. Register Access Interface

All RapidIO II IP core variations include a Register Access interface. This Avalon-MM slave interface provides access to all of the registers in the RapidIO II IP core except the Doorbell Logical layer registers.
Note: The Doorbell Logical layer registers are available only in RapidIO II IP core variations that instantiate a Doorbell Logical layer module, and you must access them through the Doorbell module's Avalon-MM slave interface.