RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents

7.2.6. NWRITE Transactions

To perform NWRITE operations, one register in the IP core must be reconfigured as shown below:
Table 185.  NWRITE_R Transactions
Module Register Address Register Name Description Value
rio 0x1040C Input/Output Slave Mapping Window 0 Control Sets the DESTINATION_ID for outgoing transactions to the value 0xCD or 0xCDCD, depending on the device ID width of the sister_rio. This value matches the base device ID of the sister_rio. Sets the write request type back to NWRITE. 32'h00CD_0000 or 32'hCDCD_0000

With these settings, any write operation presented across the Input/Output Avalon-MM slave interface is translated into a RapidIO NWRITE transaction.

The testbench generates a predetermined series of burst writes across the Input/Output Avalon-MM slave module's Avalon-MM write interface on the DUT. These write bursts are each converted into an NWRITE request packet that is sent over the RapidIO serial interface. The testbench cycles from two to 128 in steps of 8 bytes. Two tasks are run to carry out the burst writes, rw_addr_data and rw_data. The rw_addr_data task initiates the burst and the rw_data task completes the remainder of the burst. The ios_128_rd_wr_master_bfm read_write_cmd task generates the burst writes.

The sister_rio module receives the NWRITE request packets and presents them across the I/O master Avalon-MM slave interface as write transactions. The testbench calls the sister_iom128_rd_wr_slave_bfm read_write_data task to capture the written data. The written data is checked against the expected value.

The testbench also generates NWRITE transactions with an invalid destination ID if the DUT has both of these properties:
  • Includes an Avalon-ST pass-through interface
  • Has Disable destination ID checking by default turned off
In this case, the testbench validates that the DUT correctly routes these packets to the Avalon-ST pass-through interface.

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