RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

5. Signals

This chapter lists the RapidIO II IP core signals. Signals are listed with their widths. In this context, the n in [n:0] is the number of lanes minus one, so that signal[n:0] has one bit for each lane.

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