RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.2.2.1. Input/Output Avalon-MM Slave Interface Signals5.3.1.3. Input/Output Avalon-MM Slave Interface Signals

Table 64.  Input/Output Avalon-MM Slave Interface Signals
Signal Direction Description
ios_rd_wr_waitrequest Output I/O Logical Layer Avalon-MM Slave module wait request.
ios_rd_wr_write Input I/O Logical Layer Avalon-MM Slave module write request.
ios_rd_wr_read Input I/O Logical Layer Avalon-MM Slave module read request.
ios_rd_wr_address[N:0]

for N == 9, 10,..., or 31

Input I/O Logical Layer Avalon-MM Slave module address bus. The address is a quad-word address, addresses a 16-byte (128-bit) quad-word, not a byte address. You can determine the width of the ios_rd_wr_address bus in the RapidIO II parameter editor.
ios_rd_wr_writedata[127:0] Input I/O Logical Layer Avalon-MM Slave module write data bus.
ios_rd_wr_byteenable[15:0] Input I/O Logical Layer Avalon-MM Slave module byte enable.
ios_rd_wr_burstcount[4:0] Input I/O Logical Layer Avalon-MM Slave module burst count.
ios_rd_wr_readresponse Output I/O Logical Layer Avalon-MM Slave module read error response. I/O Logical Layer Avalon-MM Slave module read error. Indicates that the burst read transfer did not complete successfully.
ios_rd_wr_readdata[127:0] Output I/O Logical Layer Avalon-MM Slave module read data bus.
ios_rd_wr_readdatavalid Output I/O Logical Layer Avalon-MM Slave module read data valid.
The I/O Avalon-MM Slave module supports an interrupt line, io_s_mnt_irq, on the Register Access interface. When enabled, the following interrupts assert the io_s_mnt_irq signal:
  • Read out of bounds
  • Write out of bounds
  • Invalid write
  • Invalid read or write burstcount
  • Invalid read or write byteenable value

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