RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents

6.1.6. Maintenance Module Registers Memory Map6.3.3.1. Maintenance Module Registers Memory Map

Table 83.  Table 124.  Maintenance Module Registers Memory Map
Address Register
0x10080 Maintenance Interrupt
0x10084 Maintenance Interrupt Enable
0x10088 – 0x100FC Reserved
0x10100 Tx Maintenance Window 0 Base
0x10104 Tx Maintenance Window 0 Mask
0x10108 Tx Maintenance Window 0 Offset
0x1010C Tx Maintenance Window 0 Control
0x10110 – 0x1011C Tx Maintenance Windows 1
0x10200 Tx Port Write Control
0x10204 Tx Port Write Status
0x10210 – 0x1024C Tx Port Write Buffer
0x10250 Rx Port Write Control
0x10254 Rx Port Write Status
0x10260 – 0x1029C Rx Port Write Buffer
0x102A0 – 0x102FC Reserved

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