RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.4.1. Receiver

On the receive side, the Transport layer module receives packets from the Physical layer. Packets travel through the Rx buffer, and any errored packet is eliminated. The Transport layer module routes the packets to one of the Logical layer modules or to the Avalon-ST pass-through interface based on the packet's destination ID, format type (ftype), and target transaction ID (targetTID) header fields. The destination ID matches only if the transport type (tt) field matches.

If you turn off destination ID checking in the RapidIO II parameter editor, the Transport layer routes incoming packets from the Physical layer that are not already marked as errored according to the following rules:
  • Routes packets with unsupported ftype to the Avalon-ST pass-through interface, if the Avalon-ST pass-through interface is instantiated in the IP core variation.
  • Routes packets with a tt value that does not match the RapidIO II IP core’s device ID width support level according to the following rules:
    • If you turned on Enable 16-bit device ID width in the RapidIO II parameter editor, routes packets with an 8-bit device ID to the Avalon-ST pass-through interface, if the Avalon-ST pass-through interface is implemented in the IP core variation. If this interface is not implemented in your variation, drops the packet.
    • If you turned off Enable 16-bit device ID width in the RapidIO II parameter editor, drops packets with a 16-bit device ID.
    In any of the cases in which the packet is dropped, the Transport layer module asserts the transport_rx_packet_dropped signal.
  • Request packets with a supported ftype and a tt value that matches the RapidIO II IP core’s device ID width are routed to the Logical layer supporting the ftype. If the request packet has an unsupported ttype, the Logical layer module then performs the following tasks:
    • Sends an ERROR response for request packets that require a response.
    • Records an unsupported_transaction error in the Error Management extension registers.
  • Packets that would be routed to the Avalon-ST pass-through interface, in the case that the RapidIO II IP core does not implement an Avalon-ST pass-through interface, are dropped. In this case, the Transport layer module asserts the transport_rx_packet_dropped signal.
  • ftype=13 response packets are routed based on the value of their target transaction ID field. Each Logical layer module is assigned a range of transaction IDs. If the transaction ID of a received response packet is not within one of the ranges assigned to one of the enabled Logical layer modules, the packet is routed to the Avalon-ST pass-through interface.
Packets marked as errored by the Physical layer (for example, packets with a CRC error or packets that were stomped) are filtered out and dropped from the stream of packets sent to the Logical layer modules or pass-through interface. In these cases, the transport_rx_packet_dropped output signal is not asserted.

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