RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.2.4. Local Configuration Space Base Address 0 CSR

Table 119.  Local Configuration Space Base Address 0 CSR — Offset: 0x58
Field Bits Access Function Default
RSRV [31] RO Reserved. 1'b0
LCSBA [30:15] RO Reserved for a 34-bit local physical address. 16'h0000
LCSBA [14:0] RO Reserved for a 34-bit local physical address. 15'h0000
Note: The Local Configuration Space Base Address 0 register is hard coded to zero. If the Input/Output Avalon-MM master interface is connected to the Register Access Avalon-MM slave interface, regular read and write operations rather than MAINTENANCE operations can be used to access the processing element's registers for configuration and maintenance.

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