RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.1.1. CAR Memory Map6.3.1.1. CAR Memory Map

Table 78.  Table 105.  CAR Memory Map
Address Register
0x0 Device Identity
0x4 Device Information
0x8 Assembly Identity
0xC Assembly Information
0x10 Processing Element Features
0x14 Switch Port Information
0x18 Source Operations
0x1C Destination Operations
0x34 Switch Route Table Destination ID Limit
0x3C Data Streaming Information
Note: The CARs are not used by any of the RapidIO II IP core internal modules. They do not affect the functionality of the RapidIO II IP core. These registers are all Read-Only. Their values are set using the RapidIO II parameter editor when generating the IP core, or with configuration input signals, which should not change value during normal operation. These registers inform either a local processor or a processor on a remote end about the IP core's capabilities.

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