RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.1.7. Switch Port Information CAR

Table 111.  Switch Port Information CAR — Offset: 0x14
Field Bits Access Function Default
RSRV [31:16] RO Reserved. 16'b0
PortTotal [15:8] RO The maximum number of RapidIO ports on the processing element:
  • 8'h0 — Reserved
  • 8'h1 — 1 port
  • 8'h2 — 2 ports
  • ...
  • 8'hFF — 255 ports
0
PortNumber 35 [7:0] RO This is the port number from which the MAINTENANCE read operation accessed this register. Ports are numbered starting with 8'h0. 0
35 If the Switch Port Information CAR is accessible from multiple ports, user logic must implement shadowing of the PortNumber field.

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