RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

7.4. Transceiver Level Connections in the Testbench

The testbench for Intel® Arria® 10 , Intel® Stratix® 10 and Intel® Cyclone® 10 GX variations demonstrates one method to connect the reset controller, the TX PLL, and the RapidIO II IP core to each other.
Figure 39. RapidIO II IP Core, TX PLL, and Reset Controller Connections in Intel® Arria® 10 and Intel® Cyclone® 10 GX Testbench
Figure 40. RapidIO II IP Core, TX PLL, and Reset Controller Connections in Intel® Stratix® 10 Testbench
Table 187.  External Transceiver TX PLL Connections to RapidIO II IP Core
Signal Direction Connection Requirements
pll_powerdown Input Connect pll_powerdown to the pll_powerdown[0] output port of the reset controller.

This signal is available in Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V variations only.

pll_refclk0 Input Drive the PLL pll_refclk0 input port and the RapidIO II IP core tx_pll_refclk signal from the same clock source.
pll_locked Output Connect pll_locked to the pll_locked[n] input signal of the reset controller, for each transceiver channel n that connects to the RapidIO link.
pll_cal_busy Output Drive the pll_tx_cal_busy input signal of the reset controller.
mcgb_rst 47 Input Drive mcgb_rst from the system reset signal.
tx_bonding_clocks [6N-1:0] where N is the number of lanes in the IP core variation Output Connect the TX PLL tx_bonding_clocks output signal bits [6z+5:6z] to the RapidIO II IP core tx_bonding_clocks_chz input signal to RapidIO lane z.
47 This signal is unavailable while using Intel® Stratix® 10 devices.

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