RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.7.3. Tx Doorbell

Table 174.  Tx Doorbell Control — Offset: 0x10608
Field Bits Access Function Default
RSRV [31:2] RO Reserved. 30'h0
PRIORITY [1:0] RW Request Packet’s priority. 2’b11 is not a valid value for the priority field. An attempt to write 2’b11 to this field will be overwritten as 2’b10. 2'b00
Table 175.  Tx Doorbell — Offset: 0x1060C
Field Bits Access Function Default
LARGE_DESTINATION_ID (MSB) [31:24] RW/RO MSB of the targeted RapidIO processing element device ID if the system supports 16-bit device ID.

Reserved if the system does not support 16-bit device ID.

8'h00
DESTINATION_ID [23:16] RW Device ID of the targeted RapidIO processing element. 8'h00
INFORMATION (MSB) [15:8] RW MSB information field of the outbound DOORBELL message. 8'h00
INFORMATION (LSB) [7:0] RW LSB information field of the outbound DOORBELL message. 8'h00
Table 176.  Tx Doorbell Status — Offset: 0x10610
Field Bits Access Function Default
RSRV [31:24] RO Reserved. 8'h00
PENDING [23:16] RO Number of DOORBELL messages that have been transmitted, but for which a response has not been received. There can be a maximum of 16 pending DOORBELL messages. 8'h00
TX_FIFO_LEVEL [15:8] RO The number of DOORBELL messages in the staging FIFO plus the number of DOORBELL messages in the Tx FIFO. The maximum value is 16. 8'h00
TXCPL_FIFO_LEVEL [7:0] RO The number of available completed Tx DOORBELL messages in the Tx Completion FIFO. The FIFO can store a maximum of 16. 8'h00
Table 177.  Tx Doorbell Completion — Offset: 0x10614The completed Tx DOORBELL message comes directly from the Tx Doorbell Completion FIFO.
Field Bits Access Function Default
LARGE_DESTINATION_ID (MSB) [31:24] RO MSB of the targeted RapidIO processing element device ID if the system supports 16-bit device ID.

Reserved if the system does not support 16-bit device ID.

8'h00
DESTINATION_ID [23:16] RO Device ID of the targeted RapidIO processing element. 8'h00
INFORMATION (MSB) [15:8] RO MSB information field of the outbound DOORBELL message that has been confirmed as successful or unsuccessful. 8'h00
INFORMATION (LSB) [7:0] RO LSB information field of the outbound DOORBELL message that has been confirmed as successful or unsuccessful. 8'h00
Table 178.  Tx Doorbell Completion Status — Offset: 0x10618
Field Bits Access Function Default
RSRV [31:2] RO Reserved. 30'h0
ERROR_CODE [1:0] RO This error code corresponds to the most recently read message from the Tx Doorbell Completion register. After software reads the Tx Doorbell Completion register, a read to this register should follow to determine the status of the message.
  • 2'b00 — Response DONE status
  • 2'b01 — Response with ERROR status
  • 2'b10 — Time-out error
2'b00
Table 179.  Tx Doorbell Status Control — Offset: 0x1061C
Field Bits Access Function Default
RSRV [31:2] RO Reserved. 30'h0
ERROR [1] RW If set, outbound DOORBELL messages that received a response with ERROR status, or were timed out, are stored in the Tx Completion FIFO. Otherwise, no error reporting occurs. 1'b0
COMPLETED [0] RW If set, responses to successful outbound DOORBELL messages are stored in the Tx Completion FIFO. Otherwise, these responses are discarded. 1'b0

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