RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.6.9. Packet Time-to-Live

Table 161.  Packet Time-to-Live CSR — Offset: 0x32C
Field Bits Access Function Default
TIME_TO_LIVE [31:16] RW Maximum time duration that a packet is allowed to remain in a switch device, where the value of 0xFFFF indicates 100 ms ±34%. The RapidIO II IP core does not use the contents of this field. The field value is available on the time_to_live output signal. 16'h0000
RSRV [15:0] RO Reserved. 16'h0000

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