RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.1.5. Error Management Extensions Extended Features Block Memory Map6.3.6.1. Error Management Extensions Extended Features Block Memory Map

Table 82.  Table 153.  Error Management Extensions Extended Features Block Memory Map
Address Register
0x300 Error Management Extensions Block Header
0x304 Reserved
0x308 Logical/Transport Layer Error Detect
0x30C Logical/Transport Layer Error Enable
0x310 Logical/Transport Layer High Address Capture

Reserved — RapidIO II IP core has only 34-bit RapidIO addressing.

0x314 Logical/Transport Layer Address Capture
0x318 Logical/Transport Layer Device ID Capture
0x31C Logical/Transport Layer Control Capture
0x320 – 0x324 Reserved
0x328 Port-Write Target Device ID
0x32C Packet Time-to-Live
0x330–0x33C Reserved
0x340 Port 0 Error Detect
0x344 Port 0 Error Rate Enable
0x348 Port 0 Attributes Capture
0x34C Port 0 Packet/Control Symbol Capture 0
0x350 Port 0 Packet Capture 1
0x354 Port 0 Packet Capture 2
0x358 Port 0 Packet Capture 3
0x35C – 0x364 Reserved
0x368 Port 0 Error Rate
0x36C Port 0 Error Rate Threshold

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