RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

A. Initialization Sequence

This appendix describes the most basic initialization sequence for a RapidIO II system that contains two RapidIO II IP cores connected through their RapidIO interfaces.
To initialize the system, perform these steps:
  1. Read the Port 0 Error and Status Command and Status register (CSR) (0x00158) of the first RapidIO II IP core to confirm port initialization.
  2. Set the following registers in the first RapidIO II IP core:
    1. To set the base ID of the device to 0x01, set the Base_deviceID field (bits 23:16) or the Large_base_deviceID field (bits 15:0) of the Base Device ID register (0x00060) to 0x1.
    2. To allow request packets to be issued, write 1 to the ENA field (bit 30) of the Port General Control CSR (0x13C).
    3. To set the destination ID of outgoing maintenance request packets to 0x02, set the DESTINATION_ID field (bits 23:16) or the combined (LARGE_DESTINATION_ID MSB, DESTINATION_ID) fields (bits 31:16) of the Tx Maintenance Window 0 Control register (0x1010C) to 0x02.
    4. To enable an all-encompassing address mapping window for the maintenance module, write 1’b1 to the WEN field (bit 2) of the Tx Maintenance Window 0 Mask register (0x10104).
  3. Set the following registers in the second RapidIO II IP core:
    1. To set the base ID of the device to 0x02, set the Base_deviceID field (bits 23:16) or the Large_base_deviceID field (bits 15:0) of the Base Device ID register (0x00060) to 0x02.
    2. To allow request packets to be issued, write 1’b1 to the ENA field (bit 30) of the Port General Control CSR (0x13C).
    3. To set the destination ID of outgoing maintenance packets to 0x0, set the DESTINATION_ID field (bits 23:16) or the combined (LARGE_DESTINATION_ID MSB, DESTINATION_ID) fields (bits 31:16) of the Tx Maintenance Window 0 Control register (0x1010C) to 0x0.
    4. To enable an all-encompassing address mapping window for the maintenance module, write 1’b1 to the WEN field (bit 2) of the Tx Maintenance Window 0 Mask register (0x10104).
These register settings allow one RapidIO II IP core to remotely access the other RapidIO II IP core.

To access the registers, the system requires an Avalon® -MM master, for example a Nios® II processor. The Avalon® -MM master can program these registers. You can use the Platform Designer system integration tool, available with the Intel® Quartus® Prime software, to rapidly and easily build and evaluate your RapidIO system.

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