RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.3.5.1. IP Core Actions

In response to incoming MAINTENANCE requests on the RapidIO link that do not target the RapidIO II IP core internal register set, the RapidIO II IP core Maintenance module generates Avalon-MM requests on the Maintenance module master interface, by performing the following tasks:
  • For a MAINTENANCE read, converts the received request packet to an Avalon read request and presents it across the Maintenance Avalon-MM master interface.
  • For a MAINTENANCE write, converts the received request packet to an Avalon write transfer and presents it across the Maintenance Avalon-MM master interface.
  • For each Avalon read request the IP core presents on the Maintenance Avalon-MM master interface, the Maintenance module accepts the data response, generates a Type 8 Response packet, and presents the response packet to the Transport layer for transmission on the RapidIO link.
The Maintenance module only supports single 32-bit word transfers, that is, rdsize and wrsize = 4’b1000. If the RapidIO II IP core receives a MAINTENANCE request on the RapidIO link with a different value in this field, the IP core sends an error response packet on the RapidIO link, and no transfer occurs.
The RapidIO II IP core uses the wdptr and config_offset values in the incoming RapidIO request packet to generate the Avalon-MM address in the transaction it presents on the Maintenance module master interface, using the following formula:
usr_mnt_address = {8’h00, config_offset, ~wdptr, 2'b00}
The IP core presents the data in the RapidIO transaction payload field on the usr_mnt_writedata[31:0] bus.

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