RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.6. Error Management Registers

The RapidIO II IP core implements the Error Management Extensions registers. These registers are configured in your RapidIO II IP core variation if you turn on Enable error management extension registers on the Error Management Registers tab of the RapidIO II parameter editor.

The Error Management Extensions registers can be used by software to diagnose problems with packets that are received by the local endpoint. If enabled, the detected error triggers the assertion of std_reg_mnt_irq. Information about the packet that caused the error is captured in the capture registers. After an error condition is detected, the information is captured and the capture registers are locked until the Error Detect CSR is cleared. Upon being cleared, the capture registers are ready to capture a new packet that exhibits an error condition.

The offset values within the address space for these registers are defined by the RapidIO standard.

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