RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.3.7.3. User Sending MAINTENANCE Read Requests and Receiving Responses

Table 27.  Maintenance Interface Usage Example: Sending MAINTENANCE Read Request and Receiving Response
User Operation Device ID Width Payload Size
Send MAINTENANCE read request 16-bit 0
Receive MAINTENANCE read response 16-bit 32-bit
Figure 25. Read Transfers on the Maintenance Avalon-MM Slave InterfaceIt shows the behavior of the signals for two read transfers on the Maintenance Avalon-MM slave interface.

In the first active clock cycle of the example, user logic specifies that the active transaction is a read request, by asserting the mnt_s_read signal while specifying the source address for the read data on the mnt_s_address signal. However, the RapidIO II IP core throttles the incoming transaction by asserting the mnt_s_writerequest signal until it is ready to receive the read transaction. In the example, the IP core throttles the incoming transaction for four clock cycles. The user logic maintains the values on the mnt_s_read and mnt_s_address signals until one clock cycle after the IP core deasserts the mnt_s_waitrequest signal. In the following clock cycle, user logic sends the next read request, which the IP core also throttles for four clock cycles.

The RapidIO II IP core presents the read responses it receives on the RapidIO link as read data responses on the Maintenance Avalon-MM slave interface. The IP core presents the read data responses in the same order it receives the original read requests, by asserting the mnt_s_readdatavalid signal while presenting the data on the mnt_s_data bus.
Table 28.  Maintenance Read Request Transmit Example: RapidIO Packet Fields
Field Value Comment
ackID 6'h00 Value is written by the Physical layer before the packet is transmitted on the RapidIO link.
VC 0 The RapidIO II IP core supports only VC0.
CRF 0 This bit sets packet priority together with prio if CRF is supported. This bit is reserved if VC=0 and CRF is not supported.
prio[1:0]   The IP core assigns to this field the value programmed in the PRIORITY field of the Tx Maintenance Mapping Window n Control register for the matching address translation window n.
tt[1:0] 2'b01 The value of 1 indicates 16-bit device IDs.
ftype[3:0] 4'b1000 The value of 8 indicates a Maintenance Class packet.
destinationID[15:0]   The IP core assigns to this field based on the values programmed in the LARGE_DESTINATION_ID and DESTINATION_ID fields of the Tx Maintenance Mapping Window n Control register for the matching address translation window n.
sourceID[15:0]   The IP core assigns to this field the value programmed in the Large_base_deviceID field of the Base Device ID register (offset 0x60).
ttype[3:0] 4'b0000 The value of 0 indicates a MAINTENANCE read request.
rdsize[3:0] 4'b1000 The size and wdptr values encode the maximum size of the payload field. In MAINTENANCE transactions, the value of rdsize is always 4’b1000, which decodes to a value of 4 bytes.
srcTID[7:0]   The RapidIO II IP core generates the source transaction ID value internally to track the transaction response. The value depends on the current state of the RapidIO II IP core when it prepares the RapidIO packet.
config_offset[20:0]   Depends on the value on the mnt_s_address bus, and the values programmed in the Tx Maintenance Address Translation Window registers.
wdptr   The IP core assigns to this field the negation of mnt_s_address[0].
hop_count   The IP core assigns to this field the value programmed in the HOP_COUNT field of the Tx Maintenance Mapping Window n Control register for the matching address translation window n.

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