RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

2.7.4. Adding Transceiver Analog Settings for Arria V GZ and Stratix V Variations

In general, Intel® recommends that you maintain the default transceiver settings specified by the RapidIO II IP core. However, Arria® V GZ or Stratix® V variations require that you specify some analog transceiver settings.

After you generate your RapidIO II IP core in a Intel® Quartus® Prime project that targets an Arria® V GZ or Stratix® V device, perform the following steps:

  1. In the Intel® Quartus® Prime software, on the Assignments tab, click Assignment Editor.
  2. In the Assignment Editor, in the Assignment Name column, double click <<new>> and select Transceiver Analog Settings Protocol.
  3. In the To column, type the name of the transceiver serial data input node in your IP core variation. This name is the variation-specific version of the rd signal.
  4. In the Value column, click and select SRIO.
  5. Repeat steps 2 to 4 to create an additional assignment, In step 3, instead of typing the name of the transceiver serial data input node, type the name of the transceiver serial data output put node. This name is the variation-specific version of the td signal.

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