RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

5.1. Global Signals

Table 53.  Clock Signals
Signal Direction Description
sys_clk Input Avalon® system clock.
tx_pll_refclk Input Physical layer reference clock. Your design must drive this clock from the same source as the sys_clk input clock.

In Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX device variations, despite the signal name, this clock is the reference clock for the RX CDR block in the transceiver. In other variations, this clock is also the reference clock for the TX PLL in the transceiver.

rx_clkout Output Receive-side recovered clock. This signal is derived from the incoming RapidIO data.
tx_clkout Output Transmit-side clock.
tx_bonding_clocks_ch0[5:0] Input Transceiver channel TX input clocks for RapidIO lane 0. This signal is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX variations. Each transceiver channel that corresponds to a RapidIO lane has six input clock bits. The bits are expected to be driven from a TX PLL.
tx_bonding_clocks_ch1[5:0] Input Transceiver channel TX input clocks for RapidIO lane 1. This signal is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX 2x and 4x variations. Each transceiver channel that corresponds to a RapidIO lane has six input clock bits. The bits are expected to be driven from a TX PLL.
tx_bonding_clocks_ch2[5:0] Input Transceiver channel TX input clocks for RapidIO lane 2. This signal is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX 4x variations. Each transceiver channel that corresponds to a RapidIO lane has six input clock bits. The bits are expected to be driven from a TX PLL.
tx_bonding_clocks_ch3[5:0] Input Transceiver channel TX input clocks for RapidIO lane 3. This signal is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX 4x variations. Each transceiver channel that corresponds to a RapidIO lane has six input clock bits. The bits are expected to be driven from a TX PLL.
reconfig_clk_ch0 Input Clocks the dynamic reconfiguration interface for RapidIO lane 0. This interface is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX variations for which you turn on Enable transceiver dynamic reconfiguration.
reconfig_clk_ch1 Input Clocks the dynamic reconfiguration interface for RapidIO lane 1. This interface is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX 2x and 4x variations for which you turn on Enable transceiver dynamic reconfiguration.
reconfig_clk_ch2 Input Clocks the dynamic reconfiguration interface for RapidIO lane 2. This interface is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX 4x variations for which you turn on Enable transceiver dynamic reconfiguration.
reconfig_clk_ch3 Input Clocks the dynamic reconfiguration interface for RapidIO lane 3. This interface is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX 4x variations for which you turn on Enable transceiver dynamic reconfiguration.
Table 54.  Global Reset Signals
Signal Direction Description
rst_n Input Active-low system reset. This reset is associated with the Avalon® system clock. rst_n can be asserted asynchronously, but must stay asserted at least one clock cycle and must be de-asserted synchronously with sys_clk. To reset the IP core correctly you must also assert this signal together with the reset input signal to the Transceiver PHY Reset Controller IP core to which you must connect the RapidIO II IP core.

Intel® recommends that you apply an explicit 1 to 0 transition on the rst_n input port in simulation, to ensure that the simulation model is properly reset.

reconfig_reset_ch0 Input Resets the dynamic reconfiguration interface for RapidIO lane 0. This interface is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX variations for which you turn on Enable transceiver dynamic reconfiguration.
reconfig_reset_ch1 Input Resets the dynamic reconfiguration interface for RapidIO lane 1. This interface is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX 2x and 4x variations for which you turn on Enable transceiver dynamic reconfiguration.
reconfig_reset_ch2 Input Resets the dynamic reconfiguration interface for RapidIO lane 2. This interface is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX 4x variations for which you turn on Enable transceiver dynamic reconfiguration.
reconfig_reset_ch3 Input Resets the dynamic reconfiguration interface for RapidIO lane 3. This interface is available in Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX 4x variations for which you turn on Enable transceiver dynamic reconfiguration.

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