Product Discontinuance Notification
1. About the RapidIO II Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. RapidIO II IP Core User Guide Archives
9. Document Revision History for the RapidIO II Intel® FPGA IP User Guide
A. Initialization Sequence
B. Differences Between RapidIO II IP Core and RapidIO IP Core
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Intel® FPGA IP Evaluation Mode
2.32.4. Generating IP Cores2.32.4. Generating IP Cores
2.32.4. Generating IP Cores2.32.4. Generating IP Cores
2.5. RapidIO II IP Core Testbench Files
2.6. Simulating IP Cores
2.7. Integrating Your IP Core in Your Design
2.8. Compiling the Full Design and Programming the FPGA
2.9. Instantiating Multiple RapidIO II IP Cores in V-series FPGA devices
3.4.1. Device Identity CAR
3.4.2. Device Information CAR
3.4.3. Assembly Identity CAR
3.4.4. Assembly Information CAR
3.4.5. Processing Element Features CAR
3.4.6. Switch Port Information CAR
3.4.7. Switch Route Table Destination ID Limit CAR
3.4.8. Data Streaming Information CAR
3.4.9. Source Operations CAR
3.4.10. Destination Operations CAR
4.3.3.1. Maintenance Interface Transactions
4.3.3.2. Maintenance Interface Signals
4.3.3.3. Initiating MAINTENANCE Read and Write Transactions
4.3.3.4. Defining the Maintenance Address Translation Windows
4.3.3.5. Responding to MAINTENANCE Read and Write Requests
4.3.3.6. Handling Port-Write Transactions
4.3.3.7. Maintenance Interface Transaction Examples
4.3.3.8. Maintenance Packet Error Handling
4.3.5.3.1. User Sending Write Request
4.3.5.3.2. User Receiving Write Request
4.3.5.3.3. User Sending Read Request and Receiving Read Response
4.3.5.3.4. User Receiving Read Request and Sending Read Response
4.3.5.3.5. User Sending Streaming Write Request
4.3.5.3.6. User Receiving Streaming Write Request
6.1.1. CAR Memory Map
6.1.2. CSR Memory Map
6.1.3. LP-Serial Extended Features Block Memory Map
6.1.4. LP-Serial Lane Extended Features Block Memory Map
6.1.5. Error Management Extensions Extended Features Block Memory Map
6.1.6. Maintenance Module Registers Memory Map
6.1.7. I/O Logical Layer Master Module Registers Memory Map
6.1.8. I/O Logical Layer Slave Module Registers Memory Map
6.1.9. Doorbell Module Registers Memory Map
6.2.1.1. LP-Serial Register Block Header
6.2.1.2. Port Link Time-out Control CSR
6.2.1.3. Port Response Time-out Control CSR
6.2.1.4. Port General Control CSR
6.2.1.5. Port 0 Link Maintenance Request CSR
6.2.1.6. Port 0 Link Maintenance Response CSR
6.2.1.7. Port 0 Local AckID CSR
6.2.1.8. Port 0 Control 2 CSR
6.2.1.9. Port 0 Error and Status CSR
6.2.1.10. Port 0 Control CSR
6.3.1.1. CAR Memory Map
6.3.1.2. Device Identity CAR
6.3.1.3. Device Information CAR
6.3.1.4. Assembly Identity CAR
6.3.1.5. Assembly Information CAR
6.3.1.6. Processing Element Features CAR
6.3.1.7. Switch Port Information CAR
6.3.1.8. Source Operations CAR
6.3.1.9. Destination Operations CAR
6.3.1.10. Switch Route Table Destination ID Limit CAR
6.3.1.11. Data Streaming Information CAR
6.3.2.1. CSR Memory Map
6.3.2.2. Data Streaming Logical Layer Control CSR
6.3.2.3. Processing Element Logical Layer Control CSR
6.3.2.4. Local Configuration Space Base Address 0 CSR
6.3.2.5. Local Configuration Space Base Address 1 CSR
6.3.2.6. Base Device ID CSR
6.3.2.7. Host Base Device ID Lock CSR
6.3.2.8. Component Tag CSR
6.3.6.1. Error Management Extensions Extended Features Block Memory Map
6.3.6.2. Error Management Extensions Block Header
6.3.6.3. Logical/Transport Layer Error Detect
6.3.6.4. Logical/Transport Layer Error Enable
6.3.6.5. Logical/Transport Layer Address Capture
6.3.6.6. Logical/Transport Layer Device ID Capture
6.3.6.7. Logical/Transport Layer Control Capture
6.3.6.8. Port-Write Target Device ID
6.3.6.9. Packet Time-to-Live
6.3.6.10. Port 0 Error Detect
6.3.6.11. Port 0 Error Rate Enable
6.3.6.12. Port 0 Attributes Capture
6.3.6.13. Port 0 Packet/Control Symbol Capture 0
6.3.6.14. Port 0 Packet Capture 1
6.3.6.15. Port 0 Packet Capture 2
6.3.6.16. Port 0 Packet Capture 3
6.3.6.17. Port 0 Error Rate
6.3.6.18. Port 0 Error Rate Threshold
7.2.1. Reset, Initialization, and Configuration
7.2.2. Maintenance Write and Read Transactions
7.2.3. SWRITE Transactions
7.2.4. NREAD Transactions
7.2.5. NWRITE_R Transactions
7.2.6. NWRITE Transactions
7.2.7. Doorbell Transactions
7.2.8. Port-Write Transactions
7.2.9. Transactions Across the AVST Pass-Through Interface
7.1. Testbench Overview
The testbench generates and monitors transactions on the Avalon® -MM interfaces and Avalon® -ST interface. MAINTENANCE, Input/Output, or DOORBELL transactions are generated if you select the corresponding modules during parameterization of the IP core.
The testbench instantiates two symmetrical RapidIO II IP core variations, each associated with the Transceiver PHY Reset Controller IP core. One instance is the Device Under Test (DUT), named rio_inst. The other instance acts as a RapidIO link partner for the RapidIO DUT module and is referred to as the sister_rio module. The two instances are interconnected through their high-speed serial interfaces. In the testbench, each IP core’s td output is connected to the other IP core’s rd input.
The sister_rio module, named sis_rio_inst, responds to transactions initiated by the DUT and generates transactions to which the DUT responds. Bus functional models (BFM) are connected to the Avalon® -MM and Avalon® -ST interfaces of both the DUT and sister_rio modules, to generate transactions to which the link partner responds when appropriate, and to monitor the responses. All of the available Avalon® -MM interfaces are enabled in the block diagram of the testbench. The two IP cores communicate with each other using the RapidIO interface. The testbench initiates the following transactions at the DUT and targets them to the sister_rio module:
- SWRITE
- NWRITE_R
- NWRITE
- NREAD
- DOORBELL messages
- MAINTENANCE writes and reads
- MAINTENANCE port writes and read
Note: Your specific variation may not have all of the interfaces enabled. If an interface is not enabled, the transactions supported by that interface are not exercised by the testbench.
In addition, the RapidIO II IP core modules implement the following features:
- Multicast-event control symbol transmission and reception. The RapidIO II IP core under test generates and transmits multicast-event control symbols in response to transitions on its send_multicast_event input signal. The sister module checks that these control symbols arrive as expected.
- Disabled destination ID checking, or not, selected at configuration.
- Indication of NWRITE_R transactions that do not complete before the end of the test sequence.
Figure 39. RapidIO II IP Core Testbench
The testbench generates and checks activity across the Avalon® -MM interfaces by running tasks that are defined in the BFMs. The file tb_rio.v implements the code that performs the test transactions. The code performs a reset and initialization sequence necessary for the DUT and sister_rio IP cores to establish a link and exchange packets.