RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents

7.1. Testbench Overview

The testbench generates and monitors transactions on the Avalon® -MM interfaces and Avalon® -ST interface. MAINTENANCE, Input/Output, or DOORBELL transactions are generated if you select the corresponding modules during parameterization of the IP core.

The testbench instantiates two symmetrical RapidIO II IP core variations, each associated with the Transceiver PHY Reset Controller IP core. One instance is the Device Under Test (DUT), named rio_inst. The other instance acts as a RapidIO link partner for the RapidIO DUT module and is referred to as the sister_rio module. The two instances are interconnected through their high-speed serial interfaces. In the testbench, each IP core’s td output is connected to the other IP core’s rd input.

The sister_rio module, named sis_rio_inst, responds to transactions initiated by the DUT and generates transactions to which the DUT responds. Bus functional models (BFM) are connected to the Avalon® -MM and Avalon® -ST interfaces of both the DUT and sister_rio modules, to generate transactions to which the link partner responds when appropriate, and to monitor the responses. All of the available Avalon® -MM interfaces are enabled in the block diagram of the testbench. The two IP cores communicate with each other using the RapidIO interface. The testbench initiates the following transactions at the DUT and targets them to the sister_rio module:
  • DOORBELL messages
  • MAINTENANCE writes and reads
  • MAINTENANCE port writes and read
Note: Your specific variation may not have all of the interfaces enabled. If an interface is not enabled, the transactions supported by that interface are not exercised by the testbench.
In addition, the RapidIO II IP core modules implement the following features:
  • Multicast-event control symbol transmission and reception. The RapidIO II IP core under test generates and transmits multicast-event control symbols in response to transitions on its send_multicast_event input signal. The sister module checks that these control symbols arrive as expected.
  • Disabled destination ID checking, or not, selected at configuration.
  • Indication of NWRITE_R transactions that do not complete before the end of the test sequence.
Figure 39. RapidIO II IP Core Testbench
The testbench generates and checks activity across the Avalon® -MM interfaces by running tasks that are defined in the BFMs. The file tb_rio.v implements the code that performs the test transactions. The code performs a reset and initialization sequence necessary for the DUT and sister_rio IP cores to establish a link and exchange packets.