RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.2.1.3. RapidIO Packet Data Word Pointer and Size Encoding in Avalon® -MM Transactions

The RapidIO II IP core converts RapidIO packets to Avalon® -MM transactions. The RapidIO packet's read size, write size, and word pointer fields, and the least significant bit of the address field, are translated to the Avalon® -MM burst count and byteenable values.

Table 15.   Avalon® -MM I/O Master Read Transaction Burstcount and Byteenable
RapidIO Field Values Avalon® -MM Signal Values
rdsize (4'bxxxx) wdptr (1'bx) address[0] (1'bx) Burstcount Byteenable (16'bxxxxxxxxxxxxxxxx)
0000 0 0 1 0000_0000_1000_0000
0 1 1 1000_0000_0000_0000
1 0 1 0000_0000_0000_1000
1 1 1 0000_1000_0000_0000
0001 0 0 1 0000_0000_0100_0000
0 1 1 0100_0000_0000_0000
1 0 1 0000_0000_0000_0100
1 1 1 0000_0100_0000_0000
0010 0 0 1 0000_0000_0010_0000
0 1 1 0010_0000_0000_0000
1 0 1 0000_0000_0000_0010
1 1 1 0000_0010_0000_0000
0011 0 0 1 0000_0000_0001_0000
0 1 1 0001_0000_0000_0000
1 0 1 0000_0000_0000_0001
1 1 1 0000_0001_0000_0000
0100 0 0 1 0000_0000_1100_0000
0 1 1 1100_0000_0000_0000
1 0 1 0000_0000_0000_1100
1 1 1 0000_1100_0000_0000
0101 13 0 0 1 0000_0000_1110_0000
0 1 1 1110_0000_0000_0000
1 0 1 0000_0000_0000_0111
1 1 1 0000_0111_0000_0000
0110 0 0 1 0000_0000_0011_0000
0 1 1 0011_0000_0000_0000
1 0 1 0000_0000_0000_0011
1 1 1 0000_0011_0000_0000
011113 0 0 1 0000_0000_1111_1000
0 1 1 1111_1000_0000_0000
1 0 1 0000_0000_0001_1111
1 1 1 0001_1111_0000_0000
1000 0 0 1 0000_0000_1111_0000
0 1 1 1111_0000_0000_0000
1 0 1 0000_0000_0000_1111
1 1 1 0000_1111_0000_0000
100113 0 0 1 0000_0000_1111_1100
0 1 1 1111_1100_0000_0000
1 0 1 0000_0000_0011_1111
1 1 1 0011_1111_0000_0000
101013 0 0 1 0000_0000_1111_1110
0 1 1 0000_0000_0111_1111
1 0 1 1111_1110_0000_0000
1 1 1 0111_1111_0000_0000
1011 0 0 1 0000_0000_1111_1111
0 1 1 1111_1111_0000_0000
1 0 1 1111_1111_1111_1111
1 1 Reserved14
1100 15 0 0 2 1111_1111_1111_1111
1 0 4 1111_1111_1111_1111
110115 0 0 6 1111_1111_1111_1111
1 0 8 1111_1111_1111_1111
111015 0 0 10 1111_1111_1111_1111
1 0 12 1111_1111_1111_1111
111115 0 0 14 1111_1111_1111_1111
1 0 16 1111_1111_1111_1111
Table 16.   Avalon® -MM I/O Master Write Transaction Burstcount and Byteenable IFor wrsize value less than 4’b1100:
RapidIO Field Values Avalon® -MM Signal Values
wrsize (4'bxxxx) wdptr (1'bx) address[0] (1'bx) Burstcount Byteenable (16'bxxxx_xxxx_xxxx_xxxx)
0000 0 0 1 0000_0000_1000_0000
0 1 1 1000_0000_0000_0000
1 0 1 0000_0000_0000_1000
1 1 1 0000_1000_0000_0000
0001 0 0 1 0000_0000_0100_0000
0 1 1 0100_0000_0000_0000
1 0 1 0000_0000_0000_0100
1 1 1 0000_0100_0000_0000
0010 0 0 1 0000_0000_0010_0000
0 1 1 0010_0000_0000_0000
1 0 1 0000_0000_0000_0010
1 1 1 0000_0010_0000_0000
0011 0 0 1 0000_0000_0001_0000
0 1 1 0001_0000_0000_0000
1 0 1 0000_0000_0000_0001
1 1 1 0000_0001_0000_0000
0100 0 0 1 0000_0000_1100_0000
0 1 1 1100_0000_0000_0000
1 0 1 0000_0000_0000_1100
1 1 1 0000_1100_0000_0000
0101 16 0 0 1 0000_0000_1110_0000
0 1 1 0000_0000_0000_0111
1 0 1 1110_0000_0000_0000
1 1 1 0000_0111_0000_0000
0110 0 0 1 0000_0000_0011_0000
0 1 1 0000_0000_0000_0011
1 0 1 0011_0000_0000_0000
1 1 1 0000_0011_0000_0000
011116 0 0 1 0000_0000_1111_1000
0 1 1 0000_0000_0001_1111
1 0 1 1111_1000_0000_0000
1 1 1 0001_1111_0000_0000
1000 0 0 1 0000_0000_1111_0000
0 1 1 1111_0000_0000_0000
1 0 1 0000_0000_0000_1111
1 1 1 0000_1111_0000_0000
100116 0 0 1 0000_0000_1111_1100
0 1 1 0000_0000_0011_1111
1 0 1 1111_1100_0000_0000
1 1 1 0011_1111_0000_0000
101016 0 0 1 0000_0000_1111_1110
0 1 1 0000_0000_0111_1111
1 0 1 1111_1110_0000_0000
1 1 1 0111_1111_0000_0000
1011 0 0 1 0000_0000_1111_1111
0 1 1 1111_1111_0000_0000
1 0 1 1111_1111_1111_1111
1 1 2

First clock cycle: 1111_1111_0000_0000

Second clock cycle: 0000_0000_1111_1111

Table 17.   Avalon® -MM I/O Master Write Transaction Burstcount and Byteenable IIFor wrsize value greater than 4’b1011:
RapidIO Values Avalon® -MM Signal Values
RapidIO Field Values Payload Size is Multiple of 16 Bytes17 Burstcount Byteenable (16'hXXXX)
wrsize (4'bxxxx) address[0] (1'bx) First Cycle Intermediate Cycles Final Cycle
1100–1111 0 Yes Payload size in bytes / 16 FFFF FFFF FFFF
1 Yes Payload size in bytes / 16 plus 1 FF00 FFFF 00FF
0 No 18 FFFF FFFF 00FF
1 No 18 FF00 FFFF FFFF
13 The RapidIO link partner should avoid read requests with this rdsize value, because the resulting byteenable value is not allowed by the Avalon® -MM specification. However, if the RapidIO II IP core receives a read request with this rdsize value, the IP core issues these transactions on the I/O Logical layer Avalon® -MM master interface with the illegal byteenable values, to support systems in which user logic handles these byteenable values.
14 This combination of wdptr and rdsize values is reserved. If the RapidIO II IP core receives this combination, it sets the Unsupported Transaction bit (UNSUPPORT_TRAN) in the Logical/Transport Layer Error Detect CSR and returns an ERROR response.
15 If rdsize has a value greater than 4’b1011, and address[0] has the value of 1, the RapidIO II IP core sets the Unsupported Transaction bit (UNSUPPORT_TRAN) in the Logical/Transport Layer Error Detect CSR and returns an ERROR response.
16 The RapidIO link partner should avoid this combination of wdptr and wrsize values, because the resulting byteenable value presented on the Avalon® -MM master interface is not allowed by the Avalon® -MM specification.
17 If the packet payload is larger than the maximum size allowed for the packet wrsize and wdptr values, the RapidIO II IP core records an Illegal transaction decode error in the Error Management Extension registers and, for NWRITE_R request packets, returns an ERROR response.
18 If the payload size is not a multiple of 16 bytes, and address[0] has the value of zero, the value of burstcount is the number of 8-byte words in the packet payload, divided by two, and rounded up.

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