RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6. Software Interface

The RapidIO II IP core supports the following sets of registers that control the RapidIO II IP core or query its status:
  • Standard RapidIO capability registers — CARs
  • Standard RapidIO command and status registers — CSRs
  • Extended features registers
  • Implementation defined registers
  • Doorbell specific registers
Some of these register sets are supported by specific RapidIO II IP core layers only. This chapter organizes the registers by the layers they support. The Physical layer registers are described first, followed by the Transport and Logical layers registers.
All of the registers are 32 bits wide and are shown as hexadecimal values. The registers can be accessed only on a 32-bit (4-byte) basis. The addressing for the registers therefore increments by units of 4.
Note: Reserved fields are labeled in the register tables. These fields are reserved for future use and your design should not write nor rely on a specific value being found in any reserved field or bit.
The following sets of registers are accessible through the Register Access Avalon® -MM slave interface:
  • CARs — Capability registers
  • CSRs — Command and status registers
  • Extended features registers
  • Implementation defined registers
A remote device can access these registers only by issuing read/write MAINTENANCE operations destined for the local device. The RapidIO II IP core routes read/write MAINTENANCE requests that address the IP core registers internally.
The doorbell registers can be accessed through the Doorbell Avalon® -MM slave interface. These registers are implemented only if you turn on Enable Doorbell support in the RapidIO II parameter editor.
Table 76.  Register Access Codes
Code Description
RW Read/write
RO Read-only
RC Read to clear
RW1C Read/Write 1 to clear
UR0 Unused bits/read as 0

Did you find the information on this page useful?

Characters remaining:

Feedback Message