RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents

7.2.3. SWRITE Transactions

The next set of operations performed are Streaming Writes (SWRITE). To perform SWRITE operations, one register in the IP core must be reconfigured as shown below:
Table 183.  SWRITE Register
Module Register Address Register Name Description Value
rio 0x1040C Input/Output Slave Mapping Window 0 Control Sets the DESTINATION_ID for outgoing transactions to the value 0xCD or 0xCDCD, depending on the device ID width of the sister_rio. This value matches the base device ID of the sister_rio module. Enables SWRITE operations. 32'h00CD_0002 or 32'hCDCD_0002
With these settings, any write operation presented across the Input/Output Avalon-MM slave interface on the rio module is translated to a RapidIO Streaming Write transaction.
Note: The Avalon-MM write address must map into Input/Output Slave Window 0. However, in this example the window is set to cover the entire Avalon-MM address space by setting the mask to all zeros.
The testbench generates a predetermined series of burst writes across the Avalon-MM slave I/O interface on the DUT. These write bursts are each converted to an SWRITE request packet sent on the RapidIO serial interface. As, the Streaming Writes only support bursts that are multiples of a double word (multiple of 8 bytes), the testbench cycles from 8 to MAX_WRITTEN_BYTES in steps of 8 bytes. The ios_128_rd_wr_master_bfm read_write_cmd task generates and checks the streaming write transaction.

At the sister_rio module, the SWRITE request packets are received and translated into Avalon-MM transactions that are presented across the Input/Output master Avalon-MM interface. The testbench calls the task read_write_data of the sister_iom128_rd_wr_slave_bfm to capture the written data. The written data is then checked against the expected value by running an expect_1 task. After completing the SWRITE tests, the testbench performs NREAD operations.

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