RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.2.2.4. Input/Output Slave Translation Window Example

This section contains an example illustrating the use of I/O slave translation windows.
Figure 16. Input/Output Slave Window Translation
In this example, a RapidIO II IP core with 8-bit device ID communicates with three other processing endpoints through three I/O slave translation windows. For this example, the XAMO bits are set to 2'b00 for all three windows. The offset value differs for each window, which results in the segmentation of the RapidIO address space that is shown below:
Figure 17. Input/Output Slave Translation Window Address Mapping
In the example, the two most significant bits of the Avalon-MM address are used to differentiate between the processing endpoints.
Translation Window 0
An Avalon-MM address in which the two most significant bits have the value 2'b01 matches window 0. The RapidIO transaction corresponding to the Avalon-MM operation has a destination ID value of 0x55. This value corresponds to processing endpoint 0.
Figure 18. Translation Window 0
Translation Window 1
An Avalon-MM address in which the two most significant bits have a value of 2'b10 matches window 1. The RapidIO transaction corresponding to the Avalon-MM operation has a destination ID value of 0xAA. This value corresponds to processing endpoint 1.
Figure 19. Translation Window 1
Translation Window 2
An Avalon-MM address in which the two most significant bits have a value of 2'b11 matches window 2. The RapidIO transaction corresponding to the Avalon-MM operation has a destination ID value of 0xCC. This value corresponds to processing endpoint 2.
Figure 20. Translation Window 2

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