RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

3.1.2. Data Settings

Data Settings set the Maximum baud rate and Reference clock frequency.

Maximum Baud Rate

Maximum baud rate defines the maximum supported baud rate. The RapidIO II IP core does not support automatic baud rate discovery.

Table 8.  Baud rates supported by the RapidIO II IP core
Device Family Mode
1x, 2x 4x
Baud Rate (MBaud)
1250 2500 3125 5000 6250 1250 2500 3125 5000 6250
Intel® Cyclone® 10 GX Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Intel® Stratix® 10 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Intel® Arria® 10 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Arria® V Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Cyclone® V Yes Yes Yes Yes 8 No Yes Yes Yes Yes 8 No
Stratix® V Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Reference clock frequency defines the frequency of the reference clock for your RapidIO II IP core internal transceiver. The RapidIO II parameter editor allows you to select any frequency supported by the transceiver.

8 In the Cyclone® V device family, only Cyclone® V GT devices support the 5.0 GBaud rate.

Did you find the information on this page useful?

Characters remaining:

Feedback Message