RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.1.4. LP-Serial Lane Extended Features Block Memory Map6.2.2. LP-Serial Lane Extended Features Block Memory Map

Table 98.  CSR Memory Map
Address Register
0x200 LP-Serial Lane Register Block Header
0x210 Lane 0 Status 0 (Local)
0x214 Lane 0 Status 1 (Far-End)
0x218 Lane 0 Status 2 (Interrupt Enable)
0x21C Lane 0 Status 3 (Received CS Field Commands)
0x220 Lane 0 Status 4 (Outgoing CS Field)
0x230 – 0x280 Lane 1–3 Status

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