RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

5.2.4. Register-Related Signals

Table 61.  Register-Related SignalsThese signals are output signals that reflect useful register field values.
Signal Direction Description
master_enable Output This output reflects the value of the Master Enable bit of the Port General Control CSR, which indicates whether this device is allowed to issue request packets. If the Master Enable bit is not set, the device may only respond to requests. User logic connected to the Avalon-ST pass-through interface should honor this value and not cause the Physical layer to issue request packets when it is not allowed.
time_to_live[15:0] Output This output reflects the value of the TIME_TO_LIVE field of the Packet Time-to-Live CSR, which is the maximum time duration that a packet is allowed to remain in a switch device.
base_device_id[7:0] Output This output reflects the value of the Base_deviceID field in the Base Device ID CSR.
large_base_device_id [15:0] Output This output reflects the value of the Large_base_deviceID field in the Base Device ID CSR.

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