RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.3.5. Receive Port-Write Registers

Table 134.  Rx Port Write Control — Offset: 0x10250
Field Bits Access Function Default
RSRV [31:2] RO Reserved. 30'h0
CLEAR_BUFFER [1] RW Clear port-write buffer. Write 1 to activate. Always read 0. 1'b0
PORT_WRITE_ENA [0] RW Port-write enable. If set to 1, port-write packets are accepted. If set to 0, port-write packets are dropped. 1'b1
Table 135.  Rx Port Write Status — Offset: 0x10254
Field Bits Access Function Default
RSRV [31:6] RO Reserved. 26'h0
CLEAR_BUFFER [5:2] RO Packet payload size in number of double words. If the size is zero, the payload size is single word. 4'h0
RSRV [1] RO Reserved. 1'b0
PORT_WRITE_BUSY [0] RO Port-write busy. Set if a packet is currently being stored in the buffer or if the packet is stored and has not been read. 1'b0
Table 136.  Rx Port Write Buffer n — Offset: 0x10260 – 0x1029C
Field Bits Access Function Default
PORT_WRITE_DATA_n [31:0] RO Port-write data. This buffer is implemented in memory and is not initialized at reset. 32'hx

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