RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

5.3.3. Data Streaming Support Signals

The RapidIO II IP core provides support for your custom implementation of data streaming using the Avalon-ST pass-through interface. In addition to Error Management Extension block signals for user-defined data streaming, the IP core provides dedicated signals to read and write the Data Streaming Logical Layer Control CSR.
Table 71.  Data Streaming Support Signals
Signal Direction Description
tm_types[3:0] Output These output signals reflect the values of the fields with the corresponding names in the Data Streaming Logical Layer Control CSR at offset 0x48.
tm_mode[3:0] Output These output signals reflect the values of the fields with the corresponding names in the Data Streaming Logical Layer Control CSR at offset 0x48.
mtu[7:0] Output These output signals reflect the values of the fields with the corresponding names in the Data Streaming Logical Layer Control CSR at offset 0x48.
tm_mode_wr Input Support user logic in setting the TM_MODE field in the Data Streaming Logical Layer Control CSR at offset 0x48. 26
tm_mode_in[3:0] Input Support user logic in setting the TM_MODE field in the Data Streaming Logical Layer Control CSR at offset 0x48.26
mtu_wr Input Support user logic in setting the MTU field in the Data Streaming Logical Layer Control CSR at offset 0x48.26
mtu_in[7:0] Input Support user logic in setting the MTU field in the Data Streaming Logical Layer Control CSR at offset 0x48.26
26 To write to the register field for any of these signal pairs, drive the value on the _in signal and then set the _wr signal to the value of 1’b1. When the _wr signal has the value of 1’b1, on the rising edge of sys_clk, the value of the _in signal is written directly to the register field.

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