RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

7.2.7. Doorbell Transactions

To test DOORBELL messages, the doorbell interrupts must be enabled. To enable interrupts, the testbench sets the lower three bits in the Doorbell Interrupt Enable register located at address 0x0000_0020. The test also programs the DUT to store all of the successful and unsuccessful DOORBELL messages in the Tx Completion FIFO.

Next, the test pushes five DOORBELL messages to the transmit DOORBELL Message FIFO of the DUT. The test increments the message payload for each transaction, which occurs when the drbl_master_bfm read_write_cmd task is invoked with a ‘WRITE operation to the TX doorbell register at offset 0x0000_000C. This action programs the 16-bit message, an incrementing payload in this example, as well as the DESTINATION_ID—0xCD for an 8-bit device ID or 0xCDCD for a 16-bit device ID—which is used in the DOORBELL transaction packet.

To verify that the DOORBELL request packets have been sent, the test waits for the drbell_s_irq signal to be asserted. The test then reads the Tx Doorbell Completion register (refer to Table 6–89 on page 6–54). This register provides the DOORBELL messages that have been added to the Tx Completion FIFO. Five successfully completed DOORBELL messages should appear in that FIFO and each one should be accessible by reading the Tx Doorbell Completion register five times in succession. To perform this verification, the test invokes the read_data task defined in the instance drbl_master_bfm.

The test waits for the DUT to assert the drbell_s_irq signal, which indicates that a DOORBELL message has been received. The test then reads the five received DOORBELL messages, by calling the read_write_cmd task with a ‘READ operation to the Rx DOORBELL register at offset 0x0000_0000. The task is called five times, once for each message, to return the received DOORBELL message.

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