RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.3.3. Transmit Maintenance Registers

When transmitting a MAINTENANCE packet, an address translation process occurs, using a base, mask, offset, and control register. Two groups of four registers can exist. The two register address offsets are shown in the table titles.
Table 127.  Tx Maintenance Mapping Window n Base — Offset: 0x10100, 0x10110
Field Bits Access Function Default
BASE [31:3] RW Start of the Avalon-MM address window to be mapped. The three least significant bits of the 32-bit base are assumed to be zero. 29'h0
RSRV [2:0] RO Reserved. 3'b000
Table 128.  Tx Maintenance Mapping Window n Mask — Offset: 0x10104, 0x10114
Field Bits Access Function Default
MASK [31:3] RW Mask for the address mapping window. The three least significant bits of the 32-bit mask are assumed to be zero. 29'h0
WEN [2] RW Window enable. Set to one to enable the corresponding window. 1'b0
RSRV [2:0] RO Reserved. 2'b00
Table 129.  Tx Maintenance Mapping Window n Offset — Offset: 0x10108, 0x10118
Field Bits Access Function Default
RSRV [31:24] RO Reserved. 8'h00
OFFSET [23:0] RW Window offset 24'h0
Table 130.  Tx Maintenance Mapping Window n Control — Offset: 0x1010C, 0x1011C
Field Bits Access Function Default
LARGE_DESTINATION_ID (MSB) [31:24] RW/RO MSB of the Destination ID if the system supports 16-bit device ID.

Reserved if the system does not support 16-bit device ID.

8'h00
DESTINATION_ID [23:16] RW Destination ID. 8'h00
HOP_COUNT [15:8] RW Hop count 8'hFF
PRIORITY [7:6] RW Packet priority. 2’b11 is not a valid value for the PRIORITY field. Any attempt to write 2’b11 to this field is overwritten with 2’b10. 2'b00
RSRV [5:0] RO Reserved. 6'h0

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