RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents User Sending Streaming Write Request

Table 49.   Avalon® -ST Pass-Through Interface Usage Example: Send SWRITE Request
User Operation Operation Type RapidIO Transaction Priority Device ID Width Payload Size (Bytes)
Send streaming write request Tx SWRITE 3 8 40
In the first clock cycle of the example, the IP core asserts gen_tx_ready to indicate it is ready to sample data. In the same cycle, user logic asserts gen_tx_valid. Because both gen_tx_ready and gen_tx_valid are asserted, this clock cycle is an Avalon® -ST ready cycle. The user logic provides valid data on gen_tx_data for the IP core to sample, and asserts gen_tx_startofpacket to indicate the current value of gen_tx_data is the initial piece of the current packet (the start of packet). On gen_tx_packet_size, user logic reports the full length of the packet is 0x30, which is decimal 48, because the packet comprises eight bytes of header and 40 bytes of payload data.
Figure 35.  Avalon® -ST Pass-Through Interface SWRITE Transmit Example
The user logic provides the 40-byte payload and 8-byte header on the same bus, gen_tx_data[127:0]. Transferring these 48 bytes of information requires three clock cycles. During all of these cycles, the IP core holds gen_tx_ready high and user logic holds gen_tx_valid high, indicating the cycles are all Avalon® -ST ready cycles. In the second cycle, user logic holds gen_tx_startofpacket and gen_tx_endofpacket low, because the information on gen_tx_data is neither start of packet nor end of packet data. In the third clock cycle, user logic asserts gen_tx_endofpacket and sets gen_tx_empty to the value of 0x0 to indicate that all of the bytes of data available on gen_tx_data in the current clock cycle are valid.
In this example, the IP core does not deassert gen_tx_ready following the three ready cycles, indicating that it is ready to accept an additional transaction whenever user logic is ready to send an additional transaction. Whether or not the IP core deasserts gen_tx_ready following the three Avalon® -ST ready cycles, the next cycle is not a ready cycle, because user logic has deasserted gen_tx_valid. The initial eight bytes of the packet contain header information.
Table 50.  SWRITE Request Transmit Example: RapidIO Header Fields on the gen_tx_data Bus
Field gen_tx_data Bits Value Comment
ackID [127:122] 6'h00 Value is a don’t care, because it is overwritten by the Physical layer ackID value before the packet is transmitted on the RapidIO link.
VC [121] 0 The RapidIO II IP core supports only VC0.
CRF [120] 0 This bit sets packet priority together with prio if CRF is supported. This bit is reserved if VC=0 and CRF is not supported.
prio[1:0] [119:118] 2'b11 Specifies packet priority.
tt[1:0] [117:116] 2'b00 The value of 0 indicates 8-bit device IDs.
ftype[3:0] [115:112] 4'b0110 The value of 6 indicates a Streaming-Write Class packet.
destinationId[7:0] [111:104] 8'hDD Indicates the ID of the target.
sourceId[7:0] [103:96] 8'hAA Indicates the ID of the source.
address[28:0] [95:67] {28’h0AABBCC, 1’b1}  
wdptr [66] 1 Not used for SWRITE transactions.
xamsbs[1:0] [65:64] 2’b00 Specifies most significant bits of extended address. Further extends the address specified by the address fields by 2 bits.