RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

B. Differences Between RapidIO II IP Core and RapidIO IP Core

This appendix lists the basic differences between the RapidIO and RapidIO II IP cores.
Table 188.  Major differences between the RapidIO II IP Core and the RapidIO IP Core
Property RapidIO II IP Core RapidIO IP Core
Protocol Complies with RapidIO specification v2.2. Complies with RapidIO specifications v1.3 and v2.1.
Device Support Supports Arria® V, Cyclone® V, Stratix® V, Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX device families. Supports multiple legacy device families, in addition to Arria® V, Cyclone® V, Stratix® V, Intel® Arria® 10 and Intel® Cyclone® 10 GX device families.
Avalon® -ST interface width Avalon® -ST pass-through Tx interface has a 128-bit wide interface for data; Avalon® -ST pass-through Rx interface presents data on a 128-bit wide interface and presents packet header information on a 115-bit wide interface.

In the Rx packet header bus, the destinationID field and the sourceID field each have 16 bits. In case of an 8-bit device ID width, the upper 8 bits of each field are set to all zeroes. However, in the TX direction the destinationID and sourceID fields fit the device ID width.

Avalon® -ST pass-through Rx and Tx interfaces each have a 32-bit wide interface in a 1× variation and a 64-bit wide interface in a 4× variation. Header and data are transmitted or received on the same bus.

In both directions, the destinationID and sourceID fields fit the device ID width.

Avalon® -MM interface width I/O Logical layer Master and Slave modules each have a 128-bit wide Rx interface and a 128-bit wide Tx interface. Doorbell and Maintenance modules each have one 32-bit wide Avalon® -MM interface in each direction. I/O Logical layer Master and Slave modules in a 1× variation each have a 32-bit wide Rx interface and a 32-bit Tx interface, in a 2x variation each have a 64- bit wide Rx interface and a 64-bit Tx interface, and in a 4× variation each have a 64-bit wide Rx interface and a 64-bit Tx interface. Doorbell and Maintenance modules each have one 32-bit wide Avalon® -MM interface in each direction, in 1× and 4× variations.
I/O Logical layer Master Avalon® -MM read and write ports I/O Logical layer Master module has a single Avalon® -MM interface for read and write transactions. I/O Logical layer Master module has one Avalon® -MM interface for read transactions and a separate Avalon® -MM interface for write transactions.
I/O Logical layer Slave Avalon® -MM read and write ports I/O Logical layer Slave module has a single Avalon® -MM interface for read and write transactions. I/O Logical layer Slave module has one Avalon® -MM interface for read transactions and a separate Avalon® -MM interface for write transactions.
CRC Physical layer removes all CRC bits and padding bytes from packets received from the RapidIO link. Physical layer removes the 16-bit CRC that follows the 80th received byte of a RapidIO packet, but not the final CRC nor the padding bytes.
Behavior in SILENT state Transmitter is turned off while the initialization state machine is in the SILENT state. In 5.0 Gbaud variations, the transmitter is turned off while the initialization state machine is in the SILENT state. However, in 1.25, 2.5, and 3.125 Gbaud variations, the transmitters send a continuous stream of K28.5 characters, all of the same disparity, in the SILENT state.
Remote host access to IP core registers Handles incoming read and write MAINTENANCE requests with address in the appropriate range to the local register set, internally. Requires that your system connect the Maintenance master interface to the Register Access slave interface. The RapidIO IP core does not implement this routing internally.
Maintenance module supported operations If you include a Maintenance module in your RapidIO II IP core, it has both master and slave ports, and supports MAINTENANCE read and write operations and MAINTENANCE port-write operations.
  • For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices:

    If you include a Maintenance module in your RapidIO IP core, it has both master and slave ports, and supports MAINTENANCE read and write operations and MAINTENANCE port-write operations.

  • For other device families:

    If you include a Maintenance module in your RapidIO IP core, you can choose whether to support an Avalon® -MM master port or an Avalon® - MM slave port, or both. if your Maintenance module supports the Avalon® -MM slave port, you can independently select whether to support MAINTENANCE TX port-write operations or MAINTENANCE RX port-write operations, or both.

Registers
  • Fully complies with Part 8: Error Management Extensions Specification of the RapidIO Interconnect Specification, Revision 2.2.
  • Supports the LP-Serial Lane Extended Features registers described in RapidIO Interconnect Specification v2.2 Part 6: LP-Serial Physical Layer Specification for up to four lanes, with two implementation-specific registers per lane.
  • Various register field differences with RapidIO IP core:
    • For example, the NWRITE_RS_COMPLETED field in the I/O Slave Interrupt and I/O Slave Interrupt Enable registers is not available in the RapidIO II IP core. However, these two registers support INVALID_READ_BYTEENABLE and INVALID_READ_BURSTCOUNT interrupts.
    • For example, the information found in the PROMISCUOUS_MODE field of the Rx Transport Control register in the RapidIO IP core is found in the DIS_DEST_ID_CHK field of the Port 0 Control CSR in the RapidIO II IP core, which has no Rx Transport Control register.
The RapidIO IP core implements a subset of the optional Error Management Extensions as defined in Part 8 of the RapidIO Interconnect Specification Revision 2.1. However, because the registers defined in the Error Management Extension specification are not all implemented in the RapidIO IP core, the error management registers are mapped in the Implementation Defined Space instead of being mapped in the Extended Features Space. The RapidIO IP core does not implement the LP-Serial Lane Extended Features registers.
Interrupt signals The RapidIO II IP core generates interrupts on multiple module- and block-specific output signals. The specific triggering conditions are noted in registers, as in the RapidIO IP core. The RapidIO II IP core generates all Doorbell module specific interrupt conditions with the drbell_s_irq signal. The RapidIO IP core generates interrupts on two output signals, the sys_mnt_s_irq signal and the drbell_s_irq signal. The sys_mnt_s_irq signal indicates all interrupt conditions that the RapidIO IP core indicates in registers, except the Doorbell module specific interrupt conditions. The RapidIO IP core generates all Doorbell module specific interrupt conditions with the drbell_s_irq signal.
Byteenable value for read requests on the I/O Logical layer Master and Slave interfaces Read transactions on the I/O Logical layer Master and Slave interfaces have associated byteenable values. Read transactions on the I/O Logical layer Master and Slave interfaces have no associated byteenable value. The byteenable value is assumed to be all ones. User logic is responsible for enforcing any required byte masking in the read data it receives, and is required to return full 32- or 64-bit words of read data.
Transport layer Tx scheduling The Transport layer implements a modified round-robin scheduling algorithm to determine the next packet to accept among those available from the Avalon® -ST pass-throuh interface and the Logical layer module. Status information from the Physical layer determines whether the round-robin algorithm considers all available packets, or considers only available packets with a priority field value above a specified threshold. This threshold can also be set to allow no packets through, providing a temporary backpressure mechanism for the Physical layer to control input from the Transport layer. The Transport layer implements a round-robin scheduling algorithm to determine the next packet to accept among those available from the Avalon® -ST pass-through interface and the Logical layer modules. This algorithm does not consider the priority field values of the packets.
Number of Link-Request Attempts Before Declaring Fatal Error parameter The number of times that a RapidIO II IP core sends a link-request input-status control symbol following a link-request time-out, before declaring a fatal error, is seven. This value cannot be modified in the parameter editor. The Link-request attempts parameter allows you to specify the number of times the RapidIO IP core sends a link-request input-status control symbol following a link-request time-out, before declaring a fatal error. This parameter can have values 1 through 7. The default value in a new variation is 7.
Note: For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, this parameter is disabled, and defaulted to value 7.
Sending Link-Request Reset-Device on Fatal Errors parameter In the RapidIO II IP core, this parameter is not available. If the RapidIO II IP core identifies a fatal error, it notifies software by setting the PORT_ERR bit in the Port 0 Error and Status CSR and asserting the port_error output signal, which may be used as an interrupt output signal. However, it does not transmit link-request reset-device control symbols. The Send link-request reset-device on fatal errors option specifies that if the RapidIO IP core identifies a fatal error, it transmits four link-request control symbols with cmd set to reset-device on the RapidIO link. By default, this option is turned off. The option is available for backward compatibility, because previous releases of the RapidIO IP core implement this behavior. In any case the RapidIO IP core notifies software by setting the PORT_ERR bit in the Port 0 Error and Status CSR and asserting the port_error output signal.

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