RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.3.7.4. User Receiving MAINTENANCE Read Requests and Sending Responses

Table 29.  Maintenance Interface Usage Example: Receiving MAINTENANCE Read Request and Sending Response
User Operation Device ID Width Payload Size
Receive MAINTENANCE read request 16-bit 0
Send MAINTENANCE read response 16-bit 32-bit
The RapidIO II IP core generates read requests on the Maintenance Avalon-MM master interface when it receives Type 8 MAINTENANCE Read packets on the RapidIO link with the following properties:
  • ttype has the value of 4'b0000, indicating a MAINTENANCE Read request
  • config_offset has a value that indicates an address outside the range of the RapidIO II IP core internal register set
Figure 26. Read Transfers on the Maintenance Avalon-MM Master InterfaceIt shows the signal relationships for an example sequence of three read requests that the RapidIO II IP core presents on the Maintenance Avalon-MM master interface, and the data responses from user logic.
In the first active clock cycle, the RapidIO II IP core indicates the start of a read request by asserting the usr_mnt_read signal. Simultaneously, the IP core presents the target address on the usr_mnt_address bus.

User logic presents the read responses on the Maintenance Avalon-MM master interface by asserting the usr_mnt_readdatavalid signal while presenting the data on the usr_mnt_data bus.

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