RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.3.7.1. User Sending MAINTENANCE Write Requests

Table 24.  Maintenance Interface Usage Example: Sending MAINTENANCE Write Request
User Operation Device ID Width Payload Size
Send MAINTENANCE write request 8-bit 32-bit
To write to a register in a remote endpoint using a MAINTENANCE write request, you must perform the following actions:
  • Set up the registers.
  • Perform a write transfer on the Maintenance Avalon-MM slave interface.
Figure 23. Write Transfers on the Maintenance Avalon-MM Slave InterfaceIt shows the behavior of the signals for four write transfers on the Maintenance Avalon-MM slave interface.
In the first active clock cycle of the example, user logic specifies the active transaction to be a write request by asserting the mnt_s_write signal while specifying the write data on the mnt_s_writedata signal and the target address for the write data on the mnt_s_address signal. However, the RapidIO II IP core throttles the incoming transaction by asserting the mnt_s_writerequest signal until it is ready to receive the write transaction.
In the example, the IP core throttles the incoming transaction for five clock cycles, because it requires six clock cycles to process each write transaction. The user logic maintains the values on the mnt_s_write, mnt_s_writedata, and mnt_s_address signals until one clock cycle after the IP core deasserts the mnt_s_waitrequest signal, as required by the Avalon-MM specification. In the following clock cycle, user logic sends the next write request, which the IP core also throttles for five clock cycles. The process repeats for an additional two write requests.
Table 25.  Maintenance Write Request Transmit Example: RapidIO Packet Fields
Field Value Comment
ackID 6'h00 Value is written by the Physical layer before the packet is transmitted on the RapidIO link.
VC 0 The RapidIO II IP core supports only VC0.
CRF 0

This bit sets packet priority together with prio if CRF is supported. This bit is reserved if VC=0 and CRF is not supported.

prio[1:0] 2'b00 The IP core assigns to this field the value programmed in the PRIORITY field of the Tx Maintenance Mapping Window n Control register for the matching address translation window n.
tt[1:0] 2'b00 The value of 0 indicates 8-bit device IDs.
ftype[3:0] 4'b1000 The value of 8 indicates a Maintenance Class packet.
destinationID[7:0]   The IP core assigns to this field the value programmed in the DESTINATION_ID field of the Tx Maintenance Mapping Window n Control register for the matching address translation window n.
sourceID[7:0]   The IP core assigns to this field the value programmed in the Base_deviceID field of the Base Device ID register (offset 0x60).
ttype[3:0] 4'b0001 The value of 1 indicates a MAINTENANCE write request.
wrsize[3:0] 4'b1000 The size and wdptr values encode the maximum size of the payload field. In MAINTENANCE transactions, the value of wrsize is always 4’b1000, which decodes to a value of 4 bytes.
srcTID[7:0]   The RapidIO II IP core generates the source transaction ID value internally to track the transaction response. The value depends on the current state of the RapidIO II IP core when it prepares the RapidIO packet.
config_offset[20:0]   Depends on the value on the mnt_s_address bus, and the values programmed in the Tx Maintenance Address Translation Window registers.
wdptr   The IP core assigns to this field the negation of mnt_s_address[0].
hop_count   The IP core assigns to this field the value programmed in the HOP_COUNT field of the Tx Maintenance Mapping Window n Control register for the matching address translation window n.
payload[63:0]   The IP core assigns the value of mnt_s_writedata[31:0] to the appropriate half of this field.

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