RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents
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4.3.4. Doorbell Module

The Doorbell module is an optional component of the I/O Logical layer. The Doorbell module provides support for Type 10 packet format (DOORBELL class) transactions, allowing users to send and receive short software-defined messages to and from other processing elements connected to the RapidIO interface.

In a typical application the Doorbell module’s Avalon-MM slave interface is connected to the system interconnect fabric, allowing an Avalon-MM master to communicate with RapidIO devices by sending and receiving DOORBELL messages.

When you configure the RapidIO II IP core, you can enable or disable the DOORBELL operation feature, depending on your application requirements. If you do not need the DOORBELL feature, disabling it reduces device resource usage. If you enable the feature, a 32–bit Avalon-MM slave port is created that allows the RapidIO II IP core to receive and generate RapidIO DOORBELL messages.

Figure 28. Doorbell Module Block Diagram
This module includes a 32–bit Avalon-MM slave interface to user logic. The Doorbell module contains the following logic blocks:
  • Register and FIFO interface that allows an external Avalon-MM master to access the Doorbell module’s internal registers and FIFO buffers.
  • Tx output FIFO that stores the outbound DOORBELL and response packets waiting for transmission to the Transport layer module.
  • Acknowledge RAM that temporarily stores the transmitted DOORBELL packets pending responses to the packets from the target RapidIO device.
  • Tx time-out logic that checks the expiration time for each outbound Tx DOORBELL packet that is sent.
  • Rx control that processes DOORBELL packets received from the Transport layer module. Received packets include the following packet types:
    • Rx DOORBELL request.
    • Rx response DONE to a successfully transmitted DOORBELL packet.
    • Rx response RETRY to a transmitted DOORBELL message.
    • Rx response ERROR to a transmitted DOORBELL message.
  • Rx FIFO that stores the received DOORBELL messages until they are read by an external Avalon-MM master device.
  • Tx FIFO that stores DOORBELL messages that are waiting to be transmitted.
  • Tx staging FIFO that stores DOORBELL messages until they can be passed to the Tx FIFO. The staging FIFO is present only if you select Prevent doorbell messages from passing write transactions in the RapidIO II parameter editor.
  • Tx completion FIFO that stores the transmitted DOORBELL messages that have received responses. This FIFO also stores timed out Tx DOORBELL requests.
  • Error Management module that reports detected errors, including the following errors:
    • Unexpected response (a response packet was received, but its TransactionID does not match any pending request that is waiting for a response).
    • Request time-out (an outbound DOORBELL request did not receive a response from the target device).