RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents
Give Feedback Port Link Time-out Control CSR

Table 89.  Port Link Time-Out Control CSR — 0x120
Field Bits Access Function Default
VALUE [31:8] RW Time-out interval value for link-layer event pairs such as the time interval between sending a packet and receiving the corresponding acknowledge control symbol, or between sending a link-request and receiving the corresponding link-response. The duration of the link-response time-out is approximately equal to 4.5 seconds multiplied by the contents of this field, divided by (224 - 1). 24'hFF_FFFF
RSRV [7:0] UR0 Reserved. 8’h0