RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

3.6. Error Management Registers Settings

The Error Management Registers tab lists a single parameter, Enable error management extension registers.

If you turn on Enable error management extension registers, your RapidIO II IP core instantiates the Error Management Extensions register block defined in the RapidIO Interconnect Specification Part 8: Error Management Extensions Specification.

The RapidIO II IP core instantiates these registers at register block offset 0x300. If you do not instantiate these registers, you can specify user-defined registers at offset 0x300.

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