RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

7. Testbench

The RapidIO II IP core includes a demonstration testbench for your use. The testbench demonstrates how to instantiate the IP core in a design and includes some simple stimulus to control the user interfaces of the RapidIO II IP core.The purpose of the supplied testbench is to provide an example of how to parameterize the IP core and how to use the Avalon Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) interfaces to generate and process RapidIO transactions.

The testbench demonstrates the following functions:
  • Port initialization process.
  • Transmission, reception, and acknowledgment of packets with 8 to 256 bytes of data payload.
  • Support for 8-bit or 16-bit device ID fields.
  • Reading from the software interface registers.
  • Transmission and reception of multicast-event control symbols.
The testbench also demonstrates how to connect your RapidIO II IP core variation to the Transceiver PHY Reset Controller IP core. The RapidIO II IP core provides only a Verilog testbench. If you generate a VHDL IP core variation, you must use a mixed-language simulator or create your own testbench.

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