RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.5.3.3. User Sending Read Request and Receiving Read Response

Table 43.   Avalon® -ST Pass-Through Interface Usage Example: Sending Read Request and Receiving Response
User Operation Operation Type RapidIO Transaction Priority Device ID Width Payload Size (Bytes)
Send read request Tx NREAD 1 16 32
Receive read response Rx Response with payload 2 16 32
The behavior of the signals on the Avalon® -ST pass-through interface for this example transaction sequence is described in
  • NREAD Request Transaction
  • NREAD Response Transaction
NREAD Request Transaction
In the first clock cycle of the example, the IP core asserts gen_tx_ready to indicate it is ready to sample data. In the same cycle, user logic asserts gen_tx_valid. Because both gen_tx_ready and gen_tx_valid are asserted, this clock cycle is an Avalon® -ST ready cycle. The user logic provides valid data on gen_tx_data for the IP core to sample, and asserts gen_tx_startofpacket to indicate the current value of gen_tx_data is the initial piece of the current packet (the start of packet). On gen_tx_packet_size, user logic reports the full length of the packet is 0xC, which is decimal 12, because the packet comprises 12 bytes of header.
Figure 30.  Avalon® -ST Pass-Through Interface NREAD Request Send and Response Receive Example
The NREAD request transaction contains no payload data. The NREAD request requires a single clock cycle. During this clock cycle, user logic asserts gen_tx_endofpacket and reports on gen_tx_empty that the number of empty bytes is 4. The initial 12 bytes of the NREAD request packet contain header information.
Table 44.  NREAD Request Transmit Example: RapidIO Header Fields on the gen_tx_data Bus
Field gen_tx_data Bits Value Comment
ackID [127:122] 6'h00 Value is a don’t care, because it is overwritten by the Physical layer ackID value before the packet is transmitted on the RapidIO link.
VC [121] 0 The RapidIO II IP core supports only VC0.
CRF [120] 0 This bit sets packet priority together with prio when CRF is supported. This bit is reserved when VC=0 and CRF is not supported.
prio[1:0] [119:118] 2'b01 Specifies packet priority.
tt[1:0] [117:116] 2'b01 The value of 1 indicates 16-bit device IDs.
ftype[3:0] [115:112] 4'b0010 The value of 2 indicates a Request Class packet.
destinationId[15:0] [111:96] 16'hDDDD The value indicates the ID of the target.
sourceId[15:0] [95:80] 16'hAAAA The value indicates the ID of the source.
ttype[3:0] [79:76] 4'b0100 The value of 4 indicates an NREAD transaction.
size[3:0] [75:72] 4'b1100 The size and wdptr values encode the maximum size of the payload field. In this example, they decode to a value of 32 bytes.
transactionID[7:0] [71:64] 8'hBB Not used for NWRITE transactions.
address[28:0] [63:35] {28’h7654321, 1’b0}  
wdptr [34] 1 The size and wdptr values encode the maximum size of the payload field.
xamsbs[1:0] [33:32] 2’b00 Specifies extended address most significant bits. Further extends the address specified by the address fields by 2 bits.
NREAD Response Transaction
In the first clock cycle of the NREAD response on the Avalon® -ST pass-through interface, user logic asserts gen_rx_hd_ready and gen_rx_pd_ready, and the IP core asserts gen_rx_hd_valid and gen_rx_pd_valid, indicating it is providing valid data on gen_rx_hd_data and gen_rx_pd_data, respectively. The assertion of both the ready signal and the valid signal on each of the header and payload-data Avalon® -ST interfaces makes the current cycle an Avalon® -ST ready cycle for both header and data.
Figure 31.  Avalon® -ST Pass-Through Interface NREAD Request Send and Response Receive Example
The IP core asserts gen_rx_pd_startofpacket to indicate the current cycle is the first valid data cycle of the packet. In this clock cycle, the IP core also makes the header and the first 128 bits of payload data available on gen_rx_hd_data and gen_rx_pd_data, respectively. The 32-byte payload requires two clock cycles. In the second clock cycle of data transfer, the IP core asserts gen_rx_pd_endofpacket to indicate this is the final clock cycle of data transfer, and specifies in gen_rx_pd_empty that in the current clock cycle, all of the bytes of gen_rx_pd_data are valid. Following the clock cycles in which valid data is available on gen_rx_pd_data, the IP core deasserts gen_rx_pd_valid.
Table 45.  NREAD Response Receive Example: RapidIO Header Fields in gen_rx_hd_data Bus
Field gen_rx_hd_data Bits Value Comment
pd_size[8:0] [114:106] 9’h020 Payload data size is 0x20 (decimal 32).
VC [105] 0 The RapidIO II IP core supports only VC0.
CRF [104] 0 This bit sets packet priority together with prio when CRF is supported. This bit is reserved when VC=0 and CRF is not supported.
prio[1:0] [103:102] 2'b10 Priority of the response packet. Value must be higher than the priority value of the request packet. In this example, the response packet has a priority value of 2’b10 and the original request has a priority value of 2’b01.
tt[1:0] [101:100] 2'b01 Indicates 16-bit device IDs..
ftype[3:0] [99:96] 4'b1101 The value of 4’hD (decimal 13) indicates a Response Class packet..
destinationId[15:0] [95:80] 16’hAAAA The destinationID of the NREAD request are swapped in the response transaction.
sourceId[15:0] [79:64] 16'h0DDDD The sourceID of the NREAD request are swapped in the response transaction.
ttype[3:0] [63:60] 4'b1000 The value of 8 indicates a Response transaction with data payload.
status[3:0] [59:56] 4'b0000 The value of 0 indicates Done. The current packet successfully completes the requested transaction.
transactionID[7:0] [55:48] 8'hBB Value in the response packet matches the transactionID of the corresponding request packet.
Reserved[47:0] [47:0] 48’h0  

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