RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents Port 0 Error Rate

Table 169.  Port 0 Error Rate CSR — Offset: 0x368
Field Bits Access Function Default
ERR_RATE_BIAS [31:24] RW Specifies the rate at which the ERR_RATE_COUNTER field is decremented. This field supports the following valid values:
  • 8’h00: Do not decrement the error rate counter.
  • 8’h01: Decrement every 1 ms (±34%).
  • 8’h02: Decrement every 10 ms (±34%).
  • 8’h04: Decrement every 100 ms (±34%).
  • 8’h08: Decrement every 1 s (±34%).
  • 8’h10: Decrement every 10 s (±34%).
  • 8’h20: Decrement every 100 s (±34%).
  • 8’h40: Decrement every 1000 s (±34%).
  • 8’h80: Decrement every 10,000 s (±34%).
All other values are reserved.
RSRV [23:18] RO Reserved. 6'h0
ERR_RATE_RECOVERY [17:16] RW Specifies the additional incrementing of the ERR_RATE_COUNTER that is allowed beyond the current value of the Error rate failed threshold trigger (ERR_RATE_FAILED_THRESHOLD field of the Port 0 Error Rate Threshold CSR. This field supports the following values
  • :2’b00: Can increment 2 errors about the specified threshold.
  • 2’b01: Can increment 4 errors above the specified threshold.
  • 2’b10: Can increment 16 errors above the specified threshold.
  • 2’b11: Do not limit incrementing the error rate count.
PEAK_ERR_RATE [15:8] RW The highest value attained by the ERR_RATE_COUNTER field since the ERR_RATE_COUNTER field was last reset. 8'h00
ERR_RATE_COUNTER [7:0] RW Lower bound on the number of Physical layer errors that have been detected by the IP core, counting the errors enabled by the Port 0 Error Rate Enable CSR, saturated according to the ERR_RATE_RECOVERY mechanism, and decremented by the ERR_RATE_BIAS mechanism. This counter increments once for every clock cycle in which at least one Physical layer error is detected by the IP core. However, if the IP core detects an error in a control symbol, this field might increment twice. This field provides an indication of the Physical layer error rate. 8'h00