RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents Doorbell Module Interface Signals

Table 67.  Doorbell Module Interface Signals
Signal Direction Description
drbell_s_waitrequest Output Doorbell module wait request.
drbell_s_write Input Doorbell module write request.
drbell_s_read Input Doorbell module read request.
drbell_s_address[3:0] Input Doorbell module address bus. The address is a word address, not a byte address.
drbell_s_writedata[31:0] Input Doorbell module write data bus.
drbell_s_readdata[31:0] Output Doorbell module read data bus.
drbell_s_irq Output Doorbell module interrupt.