RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents

6.1.2. CSR Memory Map6.3.2.1. CSR Memory Map

Table 79.  Table 116.  CSR Memory Map
Address Register
0x48 Data Streaming Logical Layer Control
0x4C Processing Element Logical Layer Control
0x58 Local Configuration Space Base Address 0
0x5C Local Configuration Space Base Address 1
0x60 Base Device ID
0x68 Host Base Device ID Lock
0x6c Component Tag
Note: You must de-assert all IP reset signals and allow link initialization to access the Command and Status Register (CSR) block.

Did you find the information on this page useful?

Characters remaining:

Feedback Message