RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.7.4. Doorbell Interrupt

Table 180.  Doorbell Interrupt Enable — Offset: 0x10620
Field Bits Access Function Default
RSRV [31:3] RO Reserved 29'h0
TX_CPL_OVERFLOW [2] RW Tx Doorbell Completion Buffer Overflow Interrupt Enable 1'b0
TX_CPL [1] RW Tx Doorbell Completion Interrupt Enable 1'b0
RX [0] RW Doorbell Received Interrupt Enable 1'b0
Table 181.  Doorbell Interrupt Status — Offset: 0x10624
Field Bits Access Function Default
RSRV [31:3] RO Reserved. 29'h0
TX_CPL_OVERFLOW [2] RW1C Interrupt asserted due to Tx Completion buffer overflow. This bit remains set until at least one entry is read from the Tx Completion FIFO. After reading at least one entry, software should clear this bit. It is not necessary to read all of the Tx Completion FIFO entries. 1'b0
TX_CPL [1] RW1C Interrupt asserted due to Tx completion status 1'b0
RX [0] RW1C Interrupt asserted due to received messages 1'b0

Did you find the information on this page useful?

Characters remaining:

Feedback Message